1. Field of the Invention
The present invention relates to a structure of a thin film transistor in which its withstand voltage characteristics and leak current characteristics are improved. The present invention also relates to a method of manufacturing the thin film transistor.
2. Description of the Related Art
In recent years, there has been known a technique in which a thin film semiconductor film is formed on a glass substrate or a quartz substrate and a transistor is manufactured by using the film as an active layer. This transistor is generically referred to as a thin film transistor. The thin film transistor will be hereinafter referred to as a TFT.
In general, as a semiconductor thin film for forming an active layer of a TFT, an amorphous silicon film or a crystalline silicon film (polycrystalline film or microcrystalline film) is used. This is because a single crystal silicon film can not be formed on a glass substrate or a quartz substrate by an existing technique.
Although low withstand voltage and large OFF-state current value do not become a subject of discussion in a TFT using an amorphous silicon film since its total characteristics are also low, they become a problem in a TFT using a crystalline silicon film.
This problem is caused because the density of defects existing in the silicon film is extremely high as compared with single crystal silicon.
As means for solving the problem, there are known structures disclosed in Japanese Patent Publication No. Hei. 3-38755 and Japanese Patent Unexamined Publication Nos. Hei. 4-360580 and Hei. 5-166837.
The structures disclosed in the above publications are referred to as an LDD technique or an offset technique. In these techniques, a high resistance region, which does not function as a channel or a drain, is disposed between a channel region and a drain region, so that a high electric filed applied between the channel region and the drain region is relaxed.
At an OFF operation, the movement of carriers via defects present in the vicinity of the boundary between the channel region and the drain region is suppressed.
The type of high resistance region is roughly divided into a structure of a non-doped region (generically referred to as an offset structure) and a structure of a lightly doped region (generically referred to as an LDD structure).
Japanese Patent Unexamined Publication Nos. Hei. 4-360580 and Hei. 5-166837 disclose a technique as a method of forming a high resistance region in which an anodic oxidation film is formed on the surface of a gate electrode and the high resistance region is formed in a self-aligning manner by the thickness of the anodic oxidation film.
This method has a feature that the high resistance region can be formed with high controllability.